1. Field of the Invention
The present invention relates generally to systems on chips, and in particular to techniques for debugging fabricated systems on chips.
2. Description of the Related Art
Systems on chips (SoCs) continue to grow in complexity as increasing numbers of transistors are incorporated into SoCs. SoC implementations can include one or more processors and a variety of peripherals, all integrated onto one semiconductor substrate. The peripherals can be in various states of operation at the same time that the processor(s) are executing any number of software processes. The number of possible states in the SoC, all of which must generally provide correct operation, increases exponentially with this additional complexity. Large numbers of possible states of the SoC are typically tested and verified during the design and manufacture of the SoC to provide reasonable assurance that the design is correct and that the SoC will function as designed.
Many stages of simulation may be performed to verify the SoC design before the actual SoC is fabricated in silicon. After fabrication of the SoC, additional testing is performed to ensure proper operation. Conventional approaches for hardware debugging of silicon are inadequate and inefficient. For example, a scan chain of registers (or flip-flops) is often included in a SoC design to aid in the debugging process of a fabricated SoC. When a problem is encountered, the current state of the SoC can be scanned out of the SoC by performing a scan dump operation. However, this usually does not provide enough information to debug the problem. The engineers debugging the SoC can try re-running a test and doing successive scan dumps. However, this can create lots of superfluous data and may not capture the problem if the system timing is different between successive scan dumps. For example, 100 scan dumps may be performed on the final 100 cycles before an error occurs. Each one of these 100 scan dumps might see different system level timing such that the dump from cycle 50 may not be fully coherent with cycle 51. Additionally, it may not be possible to dump the last 100 cycles successfully if a design takes hours to lock-up and it is not possible to predict when a lock-up will occur.